Portable applications usually need different supply voltages for different functional modules to minimize power consumption. A more interesting and efficient solution is to use one converter with a single inductor to generate multiple outputs, which reduces the external components and saves cost.
There have been several kinds of single-inductor multiple-output (SIMO) switching converters reported in recent years. The converters in references [1] and [2] make use of time-multiplexing control, which suffer from large current ripples and dissipate energy during the freewheeling state. The solution in [3] employs the ordered power-distributive control which has a main channel for compensation and other sub-channels controlled just by comparators. This simplifies the control loop, but has larger ripples and is only suited for small load currents. The converter in [5] works in Continuous Conduction Mode (CCM) and adopts several Pulse Width Modulation (PWM) controllers driven by suitable linear combinations of output errors, which can sustain large load currents, but has large ripples (150 mV) and serious cross regulation (120 mV) problems. So, the existing SIMO converters realize multiple-output with some parasitic effects:                Load currents are limited by the intrinsic requirement of Discontinuous Conduction Mode (DCM) and pseudo-CCM (PCCM) control.        Large ripples and spikes, resulting from discontinuous current change on filter capacitors with parasitic series inductors.        Cross regulation: the SIMO converter can be regarded as a multi-input multi-output system with cross regulation items.        Efficiency: more switches added in the power path result in more power loss. The efficiency gets worse especially under light loads.        
In the following, considerations on SIDO switching converters are given.
A. Power Stage and Control Sequence
A conventional buck converter consists of two power switches and one inductor, which provide high efficiency power conversion. A dual-output converter is achieved by adding another two switches at the output node of the inductor, which is shown in FIG. 1. Hereby, a switch S1 switches the VLX1 terminal of the inductor L to the input voltage source Vg and a switch S2 switches the VLX1 node alternatively to ground GND. The switches S1 and S2 are controlled via signal D1.
Switches S3 and S4 are controlled via signal D2 and connect one selected output node each, i.e. V1 or V2, to the second VLX2 terminal of the inductor L.
Output capacitors C1 and C2 are charged during the phases, where the terminal VLX2 is connected to the respective output terminals, i.e. V1 or V2, and are discharged via the output load, including R1 and R2, during the phases where the respective output node is not connected to the terminal VLX2.
FIG. 2 illustrates the control sequence and the waveforms of the steady-state inductor current and output ripples in CCM. iL is a detail view of the inductor current flowing from node VLX1 to node VLX2, D1 and D2 are the control signals as shown in FIG. 1. If D1 is high, S1 is closed and S2 is opened (and vice versa), if D2 is high, S3 is closed and S4 is opened (and vice versa).
V1 and V2 are detail views of the resulting voltages at the V1 and V2 output nodes that properties will be described in more detail under “C. Ripples”.
Differing from the comparator-based distributive structure in [3], the controller here employs both PWM generators on control signal D1 and D2, which has the advantage of large load currents and comparatively low ripples. However, as pointed out in [1], there may occur serious cross regulation problems.
B. Cross Regulation
In a SIMO converter, variation of load current on one channel will affect the others, for all outputs that share a single inductor. This is the cross regulation problem, which is one of the severest challenges in SIMO converter design. To solve this problem, the converters in [1] and [2] work in DCM or PCCM with a freewheeling state of inductor current, which makes two channels independent of each other. However, this method is not suitable for the SIDO converter in CCM.
The converter in [4] regulates the common-mode voltage (VCM=(V1+V2)/2) and the differential-mode voltage (VDM=V1−V2) instead of two outputs to partly suppress the cross regulation. As shown in FIG. 3, there are two main control loops in the system: the common-mode loop which regulates the total energy by D1, and the differential-mode loop which distributes the energy in the inductor by D2. It has been analyzed in [4] that the transfer functions G21(s) and G12(s) represent for the cross regulation items.
Based on the idea of decomposing this cross regulated multi-loop system into several single-loop sub-systems with weak interactions, a further adaptive common-mode control method is proposed. Here, VCM is adjusted according to the load currents, which can be expressed as:VCM=D2V1+(1−D2)V2.  (1)
The weighted coefficient of each channel is proportional to the load current. It is reasonable that the channel which draws more current should have a larger impact on the regulation of inductor current. According to the control sequence in FIG. 2 and assuming the ripples are negligible, the small signal behavior of the SIDO power stage in FIG. 1 can be described by state space equations as:
                                          ⅆ                          ⅆ              t                                ⁡                      [                                                                                v                    1                                                                                                                    v                    2                                                                                                                    i                    L                                                                        ]                          =                                            [                                                                                                                                            -                          1                                                /                                                  R                          1                                                                    ⁢                                              C                        1                                                                                                  0                                                                                                      D                        2                                            /                                              C                        1                                                                                                                                  0                                                                                                                                -                          1                                                /                                                  R                          2                                                                    ⁢                                              C                        2                                                                                                                                                (                                                  1                          -                                                      D                            2                                                                          )                                            /                                              C                        2                                                                                                                                                                                -                                                  D                          2                                                                    /                      L                                                                                                                          -                                                  (                                                      1                            -                                                          D                              2                                                                                )                                                                    /                      L                                                                            0                                                              ]                        ⁡                          [                                                                                          v                      1                                                                                                                                  v                      2                                                                                                                                  i                      L                                                                                  ]                                +                                                                                                       [                                                                                            0                                                                                                                                    I                              L                                                        /                                                          C                              1                                                                                                                                                                            0                                                                                                                                    -                                                              I                                L                                                                                      /                                                          C                              2                                                                                                                                                                                                                                      V                              g                                                        /                            L                                                                                                                                                              (                                                                                                V                                  2                                                                -                                                                  V                                  1                                                                                            )                                                        /                            L                                                                                                                ]                                    ⁡                                      [                                                                                                                        d                            1                                                                                                                                                                            d                            2                                                                                                                ]                                                  ⁢                                                                  [                                                                                                    v                        CM                                                                                                                                                v                        DM                                                                                            ]                            =                                                                    [                                                                                                                                                      m                              1                                                        ⁢                                                          D                              2                                                                                                                                                                                          m                              2                                                        ⁡                                                          (                                                              1                                -                                                                  D                                  2                                                                                            )                                                                                                                                0                                                                                                                                                  m                            1                                                                                                                                -                                                          m                              2                                                                                                                                0                                                                                      ]                                    ⁡                                      [                                                                                                                        v                            1                                                                                                                                                                            v                            2                                                                                                                                                                            i                            L                                                                                                                ]                                                  +                                                      [                                                                                            0                                                                                                                                                                    m                                1                                                            ⁢                                                              V                                1                                                                                      -                                                                                          m                                2                                                            ⁢                                                              V                                2                                                                                                                                                                                                          0                                                                          0                                                                                      ]                                    ⁡                                      [                                                                                                                        d                            1                                                                                                                                                                            d                            2                                                                                                                ]                                                                                                          (        2        )            where m1 and m2 are additional output voltage feedback coefficients (i.e. Vfb1=m1*V1, Vfb2=m2*V2), as referred to in later figures.
Within the state space equations (2), small letters (i.e. v1, d1) refer to the small signal time dependent properties and are functions of time, wherein capital letters (i.e. V1, D1), refer to the absolute (i.e. large signal) values.
The transfer functions of power stage can be solved from equations (2). The bode plot comparison of G12(s) in FIG. 4 shows that the proposed adaptive common-mode control has about 20 dB improvement on the suppression of cross regulation in low frequency (when Vg=4 V, R1=3, R2=90Ω).
C. Ripples
A SIDO buck converter has larger output ripples than a conventional buck converter especially under heavy loads, for the current ripples of filter capacitors in SIDO converters are the total load currents. As shown in FIG. 2, the output ripples mainly consist of two parts: the charge of filter capacitors and the voltage drop on the equivalent series resistor (ESR) of capacitor.
Hereby, V1 and V2 show respective detail views of the voltages at the V1 and V2 output nodes. The voltage steps at the transition times of D2 need to be seen in conjunction with the equivalent series resistors (ESR) of the output capacitors C1 and C2 when the respective capacitors change between charging and discharging operation and vice versa, wherein the time proportional increase and decrease in the output voltages between this voltage steps is affiliated with the actual charging and discharging operation of the output capacitors.
When the inductor current switches to one channel, the filter capacitor is charged while the other is discharged. So, the ripples of two outputs are always in inverse phase.
Another serious problem is large spikes, which are caused by the rapid current change on the equivalent series inductors (ESLs) of filter capacitors when switching S3 and S4. They are even larger than output ripples in SIDO converters (e.g. about 100 mV in [6]).
FIG. 5 shows the output section of the power stage (see FIG. 1) together with a visualization of the origin of switching spikes as well as the proposed enhanced SIDO structure by adding an additional fly capacitor Cf.
As shown in FIG. 5, when the inductor current switches between two outputs, there occur large undershot and overshot spikes on filter capacitors.
Based on the conclusion that the ripples and spikes of two outputs are inverse-phased, a fly capacitor across two outputs can be added to reduce the steady state ripples. The value of the fly capacitor needs to be careful selected, since it provides an AC path between two outputs, which would deteriorate the performance of cross regulation. Analysis and simulation show that Cf=0.1C1 is a good trade-off between ripples and cross regulation (e.g. for C1=C2).